`elasticai.creator.hdl_generator.vhdl_impl`#

VHDL implementation of HDL abstractions.

Module Contents#

Wrapper for EntityTemplateDirector to match HDL protocol method names.

`create_signal`	Create a VHDL signal.
`create_null_signal`	Create a signal that doesn’t need to be defined (e.g., input ports).
`create_instance`	Create a VHDL entity instance.

class elasticai.creator.hdl_generator.vhdl_impl.VHDLTemplateDirector[source]#

Wrapper for EntityTemplateDirector to match HDL protocol method names.

Initialization

set_prototype(prototype: str) → elasticai.creator.hdl_generator.vhdl_impl.VHDLTemplateDirector[source]#

add_parameter(name: str) → elasticai.creator.hdl_generator.vhdl_impl.VHDLTemplateDirector[source]#

elasticai.creator.hdl_generator.vhdl_impl.create_signal(name: str, width: int | None = None) → elasticai.creator.ir2vhdl.Signal[source]#

Create a VHDL signal.

Args: name: The signal name. width: The signal width. If None or 1, creates a std_logic signal. Otherwise creates a std_logic_vector signal.

Returns: A VHDL signal (Signal type).

elasticai.creator.hdl_generator.vhdl_impl.create_null_signal(name: str) → elasticai.creator.ir2vhdl.Signal[source]#

Create a signal that doesn’t need to be defined (e.g., input ports).

Args: name: The signal name.

Returns: A null-defined VHDL signal (Signal type).

Create a VHDL entity instance.

Args: node: The node representing the entity to instantiate. generics: Generic values (name -> value). ports: Port connections (port_name -> signal).

Returns: A VHDL instance.