elasticai.creator.ir2verilog#

Package Contents#

Classes#

Ir2Verilog

BaseWire

Wire

NullWire

Instance

Represents a Verilog module instance.

VectorWire

Shape

PluginLoader

PluginLoader for Ir2Verilog passes.

PluginLoader

PluginLoader for Ir2Verilog passes.

Node

Extending ir.core.Node to an hdl specific node.

Edge

TemplateDirector

Director for building verilog templates.

VerilogTemplate

Functions#

type_handler

type_handler_iterable

Data#

factory

factory

Code

API#

class elasticai.creator.ir2verilog.Ir2Verilog[source]#

Initialization

__call__(root: elasticai.creator.hdl_ir.DataGraph, registry: elasticai.creator.hdl_ir.Registry, default_root_name='root') → collections.abc.Iterable[elasticai.creator.ir2verilog.ir2verilog.Code][source]#
register_static(name: str | None, fn: collections.abc.Callable[[], str]) → collections.abc.Callable[[], str][source]#
register(name: str | None, fn: elasticai.creator.hdl_ir.TypeHandler) → elasticai.creator.hdl_ir.TypeHandler[source]#
override(name: str | None, fn: elasticai.creator.hdl_ir.TypeHandler) → elasticai.creator.hdl_ir.TypeHandler[source]#
class elasticai.creator.ir2verilog.BaseWire(name: str)[source]#

Bases: abc.ABC

types: set[type[elasticai.creator.ir2verilog.language.BaseWire]]#

‘set(…)’

property name: str#
abstractmethod define() → Iterator[str][source]#
classmethod from_code(code: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
abstractmethod classmethod can_create_from_code(code: str) → bool[source]#
classmethod register_type(t: type[elasticai.creator.ir2verilog.language.BaseWire]) → None[source]#
abstractmethod make_instance_specific(instance: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
class elasticai.creator.ir2verilog.Wire(name: str)[source]#

Bases: elasticai.creator.ir2verilog.language.BaseWire

define() → Iterator[str][source]#
classmethod can_create_from_code(code: str) → bool[source]#
make_instance_specific(instance) → Self[source]#
class elasticai.creator.ir2verilog.NullWire(name)[source]#

Bases: elasticai.creator.ir2verilog.language.BaseWire

define() → Iterator[str][source]#
classmethod can_create_from_code(code: str) → bool[source]#
classmethod from_code(code: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
make_instance_specific(instance: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
class elasticai.creator.ir2verilog.Instance(node: elasticai.creator.hdl_ir.Node, parameters: dict[str, str], ports: dict[str, elasticai.creator.ir2verilog.language.BaseWire])[source]#

Represents a Verilog module instance.

Aggregates all knowledge necessary to instantiate and use a Verilog module programmatically when generating code.

Initialization

property name: str#
property implementation: str#
define_signals() → Iterator[str][source]#

Generate wire definitions for all ports.

instantiate() → Iterator[str][source]#

Generate Verilog module instantiation code.

class elasticai.creator.ir2verilog.VectorWire(name: str, width: int)[source]#

Bases: elasticai.creator.ir2verilog.language.BaseWire

property width: int#
define() → Iterator[str][source]#
classmethod can_create_from_code(code: str) → bool[source]#
make_instance_specific(instance: str) → Self[source]#
elasticai.creator.ir2verilog.type_handler(name: str | None, fn: elasticai.creator.hdl_ir.NonIterableTypeHandler) → elasticai.creator.hdl_ir.NonIterableTypeHandler[source]#
elasticai.creator.ir2verilog.type_handler_iterable(name: str | None, fn: elasticai.creator.hdl_ir.TypeHandler) → elasticai.creator.hdl_ir.TypeHandler[source]#
class elasticai.creator.ir2verilog.Shape(*values: int)[source]#

Initialization

values are interpreted as one of the following:

  • width

  • depth, width

  • depth, width, height

Usually width is kernel_size, depth is channels

classmethod from_tuple(values: elasticai.creator.hdl_ir.ShapeTuple | list[int]) → elasticai.creator.hdl_ir.Shape[source]#
to_tuple() → elasticai.creator.hdl_ir.ShapeTuple[source]#
to_list() → list[int][source]#
__getitem__(item)[source]#
size() → int[source]#
ndim() → int[source]#
property depth: int#
__eq__(other)[source]#
property width: int#
property height: int#
__repr__() → str[source]#
elasticai.creator.ir2verilog.factory#

‘IrFactory(…)’

class elasticai.creator.ir2verilog.PluginLoader(lowering: elasticai.creator.ir2verilog.ir2verilog.Ir2Verilog)[source]#

Bases: elasticai.creator.plugin.PluginLoaderBase

PluginLoader for Ir2Verilog passes.

Initialization

filter_plugin_dicts(plugins: collections.abc.Iterable[dict[str, Any]]) → collections.abc.Iterable[dict[str, Any]][source]#
load_symbol(symbol: elasticai.creator.ir2verilog.ir2verilog.PluginSymbol) → None[source]#
get_symbols(specs: collections.abc.Iterable[elasticai.creator.ir2verilog.ir2verilog.PluginSpec]) → collections.abc.Iterable[elasticai.creator.ir2verilog.ir2verilog.PluginSymbol][source]#
class elasticai.creator.ir2verilog.PluginLoader(lowering: elasticai.creator.ir2verilog.ir2verilog.Ir2Verilog)[source]#

Bases: elasticai.creator.plugin.PluginLoaderBase

PluginLoader for Ir2Verilog passes.

Initialization

filter_plugin_dicts(plugins: collections.abc.Iterable[dict[str, Any]]) → collections.abc.Iterable[dict[str, Any]][source]#
load_symbol(symbol: elasticai.creator.ir2verilog.ir2verilog.PluginSymbol) → None[source]#
get_symbols(specs: collections.abc.Iterable[elasticai.creator.ir2verilog.ir2verilog.PluginSpec]) → collections.abc.Iterable[elasticai.creator.ir2verilog.ir2verilog.PluginSymbol][source]#
elasticai.creator.ir2verilog.factory#

‘IrFactory(…)’

class elasticai.creator.ir2verilog.Node[source]#

Bases: elasticai.creator.ir.Node, typing.Protocol

Extending ir.core.Node to an hdl specific node.

This node contains all knowledge that we need to create and use an instance of an hdl component. However, this becomes a little bit complicated because vhdl differentiates between

Attributes:

implementation:: The name of the implementation, e.g., entity name in vhdl or module name for verilog, will be used to derive the architecture name. E.g., if the implementation is "adder", we will instantiate the entity work.adder(rtl). CAUTION: This behaviour is subject to change. Future versions might require the full entity name

property implementation: str#
property input_shape: elasticai.creator.hdl_ir.Shape#
property output_shape: elasticai.creator.hdl_ir.Shape#
class elasticai.creator.ir2verilog.Edge[source]#

Bases: elasticai.creator.ir.Edge, typing.Protocol

property src_dst_indices: tuple[tuple[int | str, int | str], ...]#
elasticai.creator.ir2verilog.Code: TypeAlias#

None

class elasticai.creator.ir2verilog.TemplateDirector[source]#

Director for building verilog templates.

Most methods correspond to verilog language constructs. Building the final template can be expensive! Typically you only want to do this once. E.g.:

from string import Template
from elasticai.creator.ir2verilog import type_handler, Code, TemplateDirector, Implementation

class _ExplodingTemplate:
    def substitute(self, params):
        raise RuntimeError("Template not initialized!")

_template = None

@type_handler
def fir_filter(impl: Implementation) -> Code:
    global _template
    if _template is None:
        _template = (
            TemplateDirector()
            .define_scoped_switch("USE_EXT_WEIGHTS", False)
            .define_scoped_switch("USE_EXT_MAC", False)
            .parameter("BITWIDTH")
            .parameter("LENGTH")
            .localparam("FILT_COEFFS")
            .localparam("NUM_MULT_UNIT")
            .add_module_name()
            .set_prototype(res.read_text(package_path, "verilog/filter_fir_full.v"))
            .build()
        )
    return _template.substitute(impl.attributes)

Initialization

reset() → Self[source]#
set_prototype(prototype: str) → Self[source]#
parameter(name: str) → Self[source]#
localparam(name: str) → Self[source]#
replace_module_of_instance(module_name: str, new_name: str) → Self[source]#
replace_instance_name(module_name: str, new_name: str) → Self[source]#
define_scoped_switch(name: str, default: bool) → Self[source]#

Add a switch for a define that is scoped to the module name.

The switch will be prefixed with the value that users provide as module_name to the render call.

Parameters:

  • name – String with name of the switch/define name

  • default – Setting switch for defining output state (True=set, False=undefine)

add_module_name() → Self[source]#
build() → elasticai.creator.ir2verilog.templates.Template[source]#
class elasticai.creator.ir2verilog.VerilogTemplate(template: string.Template, defines: dict[str, bool], module_name: dict[str, str])[source]#

Initialization

substitute(params: dict[str, str | bool] = {}, /, **kwargs: Any) → str[source]#