elasticai.creator.hdl_generator.verilog_impl#

Verilog implementation of HDL abstractions.

Module Contents#

Classes#

VerilogTemplateDirector

Wrapper for TemplateDirector to match HDL protocol method names.

Functions#

create_signal

Create a Verilog wire.

create_null_signal

Create a wire that doesn’t need to be defined (e.g., input ports).

create_instance

Create a Verilog module instance.

API#

class elasticai.creator.hdl_generator.verilog_impl.VerilogTemplateDirector[source]#

Bases: elasticai.creator.hdl_generator.protocols.HDLTemplateDirector

Wrapper for TemplateDirector to match HDL protocol method names.

Initialization

set_prototype(prototype: str) → elasticai.creator.hdl_generator.verilog_impl.VerilogTemplateDirector[source]#
add_parameter(name: str) → elasticai.creator.hdl_generator.verilog_impl.VerilogTemplateDirector[source]#
build() → elasticai.creator.hdl_generator.protocols.Template[source]#
elasticai.creator.hdl_generator.verilog_impl.create_signal(name: str, width: int | None = None) → elasticai.creator.ir2verilog.BaseWire[source]#

Create a Verilog wire.

Args: name: The wire name. width: The wire width. If None or 1, creates a single-bit wire. Otherwise creates a vector wire.

Returns: A Verilog wire (BaseWire type).

elasticai.creator.hdl_generator.verilog_impl.create_null_signal(name: str) → elasticai.creator.ir2verilog.BaseWire[source]#

Create a wire that doesn’t need to be defined (e.g., input ports).

Args: name: The wire name.

Returns: A null wire (BaseWire type).

elasticai.creator.hdl_generator.verilog_impl.create_instance(node: elasticai.creator.hdl_ir.Node, parameters: dict[str, str], ports: dict[str, elasticai.creator.ir2verilog.BaseWire]) → elasticai.creator.hdl_generator.protocols.HDLInstance[source]#

Create a Verilog module instance.

Args: node: The node representing the module to instantiate. parameters: Parameter values (name -> value). ports: Port connections (port_name -> wire).

Returns: A Verilog instance that conforms to HDLInstance protocol.