elasticai.creator.ir2verilog.language#

Module Contents#

Classes#

BaseWire

NullWire

Wire

VectorWire

Instance

Represents a Verilog module instance.

API#

class elasticai.creator.ir2verilog.language.BaseWire(name: str)[source]#

Bases: abc.ABC

types: set[type[elasticai.creator.ir2verilog.language.BaseWire]]#

‘set(…)’

property name: str#
abstractmethod define() → Iterator[str][source]#
classmethod from_code(code: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
abstractmethod classmethod can_create_from_code(code: str) → bool[source]#
classmethod register_type(t: type[elasticai.creator.ir2verilog.language.BaseWire]) → None[source]#
abstractmethod make_instance_specific(instance: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
class elasticai.creator.ir2verilog.language.NullWire(name)[source]#

Bases: elasticai.creator.ir2verilog.language.BaseWire

define() → Iterator[str][source]#
classmethod can_create_from_code(code: str) → bool[source]#
classmethod from_code(code: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
make_instance_specific(instance: str) → elasticai.creator.ir2verilog.language.BaseWire[source]#
class elasticai.creator.ir2verilog.language.Wire(name: str)[source]#

Bases: elasticai.creator.ir2verilog.language.BaseWire

define() → Iterator[str][source]#
classmethod can_create_from_code(code: str) → bool[source]#
make_instance_specific(instance) → Self[source]#
class elasticai.creator.ir2verilog.language.VectorWire(name: str, width: int)[source]#

Bases: elasticai.creator.ir2verilog.language.BaseWire

property width: int#
define() → Iterator[str][source]#
classmethod can_create_from_code(code: str) → bool[source]#
make_instance_specific(instance: str) → Self[source]#
class elasticai.creator.ir2verilog.language.Instance(node: elasticai.creator.hdl_ir.Node, parameters: dict[str, str], ports: dict[str, elasticai.creator.ir2verilog.language.BaseWire])[source]#

Represents a Verilog module instance.

Aggregates all knowledge necessary to instantiate and use a Verilog module programmatically when generating code.

Initialization

property name: str#
property implementation: str#
define_signals() → Iterator[str][source]#

Generate wire definitions for all ports.

instantiate() → Iterator[str][source]#

Generate Verilog module instantiation code.